性能.低功耗的CMOS动态逻辑运算电路毕业论文文献翻译.doc

题目：高性能.低功耗的CMOS动态逻辑运算电路摘要：本文介绍了一种应用CMOS的动态逻辑的高性能低功耗的运算电路的设计方法，并分析了它在实际应用中当技术参数改变时的灵敏度。这个提出的动态逻辑序列允许在它的输入信号作用之前在运算块内存在一个估计值，并且当输入信号到达时快速的得出一个最终的值。这种逻辑运算序列非常适合关键路径是大量（）组成的运算电路。此外，提出的这个电路在由于低时滞和动态功耗引起的高输出和高开关频率影响时，表现出更好的性能。试验表明，对于实际电路，当出现对于动态多米诺CMOS的技术的供电电源，温度，容性负载和过程变化更低的灵敏度要求时，动态逻辑方法在低功耗时能提供更小的持续时间上的延迟（3.5倍），更低的能量损耗（55%），相似的叠加延迟，能量损耗和产生有功区域（只升高8%）。关键字：动态逻辑，CMOS数字集成电路，CMOS逻辑电路，低功率运算电路，高速运算电路文章概要：1.序言2.操作说明3.性能效果3.1电路结构3.2给定的结构和动态多米诺CMOS的比较4.总结致谢参考文献1 序言多米若CMOS广泛应用于高频集成电路。和完全互补的静态CMOS逻辑1和2相比，它减少了计数装置和硅面积，并且提高了性能。然而，动态多米诺逻辑电路的主要缺点是由于开关活动时钟负载3而导致功耗过度。为了处理动态逻辑的过多功耗，通用的设计方法是在延迟关键路段的电路4 , 5 , 6 , 7和8之间交换能量。它是通过一系列的动态和静态电路设计方式4和5，并且使用双电源电压7 ,双晶体管VT的8来实现的。5中加法器的设计是在三个静态门中散放两个动态门。6的工作方式应用了建筑学结构技术来降低短路电流和过渡活动.7为了得到逻辑值在设计上应用了高电平，而用低电平来记录动态逻辑。8中放大器设计的动态逻辑是使用低压VT的高速磁心大于80% 的设备宽度。本文所用的是一种新的动态逻辑设计方法。它与动态多米诺CMOS电路相比，由于具有非常深的逻辑深度，所以提高了运算电路的特性，降低了功耗。这种动态逻辑方案已经被作者成功地在砷化镓集成电路设计应用。这种设计方式为了动态电路作用在多米若时，会产生新的特性，比如在输入有效之前，闸门开始赋值。这个结果在计算模块中赋值非常快。此外,众所周知的问题,与多米诺逻辑1 9 , 10相比 ,如逻辑非反的限制, 由于电荷再分配以及需要逆变器输出而完全消除,从而减少了芯片面积和延误, 提高了性能。这种动态逻辑显示出较高的设计灵活性; 它可以用来在多米诺形式的级联阶段,不同的设计, 多输出逻辑与迭代网络11和12 . 它也可以与流水线快速动态锁存9。为了证明这种动态逻辑在实际应用中的实用性, 目前,我们设计了一套加法比较器来和动态多米诺CMOS的一系列相应的加法器进行特性的比较。我们根据UMC实现1.2 v/3.3五1p8m逻辑高速过程，得到了RCA结构的模拟结果。我们设计了低功耗和高速应用的多个版本的建议结构. 设计及灵敏度分析一个版本低功率CMOS结构一直在13中研究着，其中包括CMOS的容性负载,温度,电源,制程变异和噪声耦合等需要考虑的因素。本文发展了这种动态逻辑模式，并且从高速和应用复位相电压vres =0和VCC/ 2得到低功耗的结构进行了敏感性分析。2 操作说明图1（a）给出了所提出的逻辑形式的典型门的基本结构。它包括一个NMOS逻辑网络（NMOS 块），一个用来将输出节点降为低逻辑水平的晶体管(Tr)和一个提高PMOS负载的晶体管(Tp)，(Tr) 和(Tp)都被时钟信号()控制。这个版本的电路图完全显示(31K)图1（a）:所提出的逻辑形式的门的基本结构，长链逆变器 。（b）晶体管电路图。（c）逆变器从第1阶段（N1）到第29阶段（N29）的输出电压的乘积。 CMOS内部提出的电路的工作的基本原理14已经给出，这里我们证明一下。当处于高阶时，输出节点通过Tr接地。当降低，Tr关断。输出节点的逻辑有条件的或者变高或者变低。如果逻辑网络的赋值升高,输出节点的值将趋近与Vcc（反向逻辑），否则，它将变低。因为给定的逻辑形式的输出复位为低逆变需要恢复输出节点极性的要求，消失了。 对于一个长链逆变器的考虑在图1（b）中给出。当时间信号降低，级联门的输出开始上升到阈值电压VTH（图1（c）。在这个电压下，电路中所有的门都处于高增益。这一特性使提出的电路可以和其他的动态逻辑电路区别开来。在VTH这点，输入节点的任意小的变动都会在输出节点的电压上产生一个快速的变化。在其他所有的逻辑设计形式中，为了让输出节点开始波动，输出都需要穿越阈值电压。然而，当一个门有了有效的输入时，门极的输出只能从VTH 到 VOH 或者VOL做有限的变化。当给定逻辑的速度再高一些便会导致波动时滞从低到高或者高到低的变化。 这种基于提出的逻辑设计形式的电路在设计时的主要挑战是，对于级联电路结构怎样保证VTH的稳定性，这对于所提出电路在快速逻辑赋值和高性能方面至关重要。3.性能效果3.1电路结构 为了在性能和功耗之间寻求一个平衡点，本文提出了两个基本设计结构，并在图2中给出。这两个设计结构来自两个不同的逻辑形式。pseudo-NMOS（高速应用，图2（a）和（b）和标准完全互CMOS（功耗低，图2（c）和（d）.这些基本的设计结构每一种都能在两种情况下操作：复位相电压等于0 (Vres=0) 或者Vcc/2 (Vres=Vcc/2)。根据图1（c）,我们发现起始阶段和其他阶段的作用不一样，因为它们没有足够的时间来到达VTH这点。然而，当Vres=Vcc/2时,和初始阶段在电压上的这种差别消失了。这个版本的电路图完全显示(32K)表2。提出的设计结构。(a) HS0: Vres=0的高速设计结构。(b) HS06: Vres=Vcc/2的高速设计结构。(c) LP0: Vres=0的低功耗设计结构。(d) LP06: Vres=Vcc/2 的低功耗设计结构。3.2给定的结构和动态多米诺CMOS的比较 为了比较提出的结构和动态多米诺CMOS结构，采用具有仿真作用的长链逆变器。我们根据UMC选用一个CMOS，每个输出端有一个10 fF的容性负载，应用理想温度参数。这个传播时滞的值tp通过20个阶段的仿真获得，并列于表1中（tp测量时是不断从高到低或从低到高变化的）。表1同时还给出了tp的平均值和动态多米诺CMOS，标准CMOS和pseudo-NMOS和tp相比的速度上升值。表1提出的设计电路和标准CMOS，pseudo-NMOS，动态多米诺CMOS比较的电路延迟参数的仿真结果。参数CMOS LP0 LP06 Pseudo NMOSDominoHS0HS06tplh (ns)2.2340.8630.7761.8230.6200.401tphl (ns)2.2470.789 0.6811.8612.5950.6900.468tp (ns)2.2400.8260.7281.8422.5950.6550.434tp ratio0.9473.1423.5651.40913.9625.979对于这个给定的结构在大量的阶段的电路中工作，要特别注意在所有的中间阶段避免不同种类的容性负载，这是为了确所有节点的电压都要和阈值电压VTH一致。为了给定的低功率设计结构Vres=0，异种容性负载在级联特性作用的中间各个的阶段的影响在图3中做了表述。在这个例子中，一个额外的1 fF的电容在第11阶段时加在了输出上，这个额外的负载在第11阶段的时候延迟了电压增加到VTH的时间，这反过来在随后的阶段又导致了逻辑赋值的延迟造成拟议动态逻辑逆变器表现为一个动态的CMOS逻辑或门。这个版本的电路图完全显示(27K)图3，异性负载在给定的设计结构逆变级联的作用的影响。Vref=0的低功率。总之，提出的这个动态逻辑模式非常适合应用于关键路径是由一个大的级联逆变门组成的电路。许多算术运算,如加法器,乘法器, FIR和其他类似结构都为了完成拟定的逻辑而清除了候选的。此外,基于提出的动态逻辑模式的电路因为在高扇出和高开关频率的情况下仍能提供更低的延迟和动态能量损耗而优势明显。拟定逻辑中更低的迟滞扰动和相负载非常适合应用于通过互联磁滞来提高深管线阶段有限制的应用场合。4总结在这篇文章里，我们提出了一个CMOS技术的新的动态逻辑模式。这个提出的结构适合高速或者低功率的逻辑深度深的电路，比如高性能的RCAs电路。我们已经设计了一些RCAs来给拟定的加法器结构的性能赋值，并且和那些高性能的加法器在技术参数上进行比较，比如动态多米诺CMOS。仿真结果表明，这种提出的加法器结构技术参数和电容耦合产生的噪声等方面的变化不是很敏感。应用了拟定的高速结构的应用电路在传播时间延迟方面强于动态多米诺CMOS5.6倍。数据的优越性增加了54%，而能源消耗的比特率为更高的54%。低功率版本的提议结构在传播时滞方面优于动态多米诺CMOS3.5倍，数据优越性是8.7%，降低能源消耗的比特率约55%。致谢这项工作得到了MIC，大韩民国的支持参考文献1 J. M. Rabaey, A. Chandrakasan and B. Nikolic, 数字集成电路，( 2002)待添加的隐藏文字内容12 P.E. Gronowski, W.J. Bowhill, R.P. Preston, M.K. Gowan and R.L. Allmon高性能微处理器设计，IEEE集成电路研讨会，实际电路33 ( 5 ) ( 1998 ). 676-686页3 R. Zimmerman and W. Fichtner, Low-power logic styles:CMOS相的传输晶体管逻辑，实际电路32 (7) (1997), 10791090页4 S. Mathew, M. Anders, R. Krishnamurthy, S. Borkar, 4 GHz的130 nm的地址机组与32位元稀疏树加法核心程序，IEEE集成电路研讨会，檀香山 126127页5 S. Mathew, M. Anders, R. Krishnamurthy and S. Borkar, 4 GHz的130 nm的地址机组与32位元稀疏树加法核心程序，实际电路38 (5) (2003), 689695页6 Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Sha and J. Chung。一种新型多型低功耗全加法器。7 R.K. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B. Chatterjee, M. Sachdev, S. Borkar。双电源电压超频5 GHz的130 nm的整数执行核心程序8 S. Vangal, Y. Hoskote, D. Somasekhar, V. Erraguntla, J. Howard, G. Ruhl, V. Veeramachaneni, D. Finan, S. Mathew, N. Borkar, 5 GHz的浮点乘法累加器90纳米双速的CMOS9 S. Nooshabadi and J.A. Montiel-Nelson, 砷化镓的一种高性能逻辑模式。10 J.L. Rossello, C. de Benito and J. Segura。紧凑门级能源和延迟模型动态CMOS门级。11，I.S. Hwang and A.L. Fisher，紧凑超快32位CMOS加法多输出多米诺逻辑12 N.J. Jha and Q. Tong, 测试多输出多米诺逻辑铸模CMOS电路13 . Navarro-Botello, J.A. Montiel-Nelson and S. Nooshabadi, 低功耗和高性能运算电路匮CMOS逻辑模式14 V. Navarro-Botello, J.A. Montiel-Nelson, S. Nooshabadi, 低功率运算电路匮动态CMOS逻辑 模式英文原文：High performance low power CMOS dynamic logic for arithmetic circuits Abstract This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates . Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies. Keywords: Dynamic logic; CMOS digital integrated circuits; CMOS logic circuits; Low power arithmetic circuits; High speed arithmetic circuits Article Outline 1. Introduction 2. Principle of operation 3. Performance results 3.1. Proposed circuit structures 3.2. Comparison of the proposed structure vs. the dynamic domino CMOS4. Conclusion Acknowledgements References1. Introduction Domino CMOS is widely used in high performance integrated circuits. It reduces the device count and silicon area, and improves performance when compared to the standard fully complementary static CMOS logic 1 and 2. However, the major drawback with the domino dynamic logic circuit is its excessive power dissipation due to the switching activity and the clock load 3. To deal with the excessive power dissipation of the dynamic logic, the current design methodologies trade power for performance in the delay critical sections of the circuit 4, 5, 6, 7 and 8. This is achieved through a mix of dynamic and static circuit styles 4 and 5, use of dual supply voltages 7, and dual VT transistors 8. The adder design in 5 intersperses two dynamic gates between three static gates. The work in 6 uses the architectural techniques to reduce the short circuit currents and transition activities. The dynamic design in 7 uses a high supply voltage for the logic evaluation, and low supply voltage for clocking the dynamic logic. The adder design in 8 uses dynamic logic, with more than 80% of the device widths in the high-speed core employ low-VT. This paper proposes a new dynamic logic family that improves the performance of arithmetic circuits, with a very long logic depth, while reducing the power dissipation, when compared with the dynamic domino CMOS circuits. The proposed dynamic logic was successfully employed, by the authors, for integrated circuits in GaAs technology 9. The proposed logic family works on domino concept for dynamic circuits, with the added feature that gates commence evaluation even before all their inputs are valid. This fact results in very fast evaluation time in the computational blocks. Furthermore, the well known problems associated with the domino logic 1, 9 and 10such as the limitation of non-inverting only logic, charge redistribution and the need for output invertersare completely eliminated, thus reducing the chip area and delay, and improving the performance. The proposed dynamic logic shows high design flexibility; it can be used in domino-like cascaded stages, differential style, and multiple output logic with iterative networks 11 and 12. It can also be pipelined with fast dynamic latches 9. In order to prove the usefulness of the proposed logic family in practical applications, we present the design of a set of adders and compare their features with a corresponding set of adders in the dynamic domino CMOS. We present the simulation results of the ripple carry adder (RCA) structures, for the implementation on 1.2 V/3.3 V 1P8M logic high speed process from UMC. We have designed multiple versions of the proposed structures for low power and high speed applications. Design and sensitivity analysis of one version of low power structures (with the reset phase voltage of 0 V, (Vres=0) in CMOS technology against the capacitive load, temperature, power supply, process variation and noise coupling, has been studied in 13. This paper extends the proposed dynamic logic family and the sensitivity analysis to high speed and low power structures using the reset phase voltages of Vres=0 and Vcc/2. 2. Principle of operation The basic structure of a typical gate in the proposed logic family is shown in Fig. 1(a). It consists of an NMOS logic network (NMOS block), an NMOS transistor (Tr) for resetting the output node to low logic level, together with a pull up PMOS load transistor (Tp). Tr and Tp are controlled by the clock signal (). Display Full Size version of this image (31K)Fig. 1. (a) Basic structure of a gate in the proposed dynamic logic family. Long chain of inverters; (b) transistor level circuit diagram; and (c) plot of the output voltages from 1st stage (N1) to 29th stage (N29) of inverters. The basic principle of operation of the proposed circuit in CMOS was presented in 14 and is briefed here. During the high phase of (reset phase), the output node is pulled to ground (GND) through Tr. When goes low (evaluation phase), Tr is turned off, and the output node conditionally evaluates to either high or low logic levels. If the logic network evaluates to high, the out node is pulled up toward Vcc (inverting logic), otherwise, it will remain low. Since in the proposed logic family the output is reset to low, the need for inverters to restore the polarity of the output node is eliminated. Consider a long chain of inverters as shown in Fig. 1(b). When the clock signal falls, the outputs of the cascaded gates begin to rise to the gate threshold voltage VTH (Fig. 1(c). At this voltage point all gates in the circuit are in a high gain point. This feature distinguishes the proposed logic family from the other dynamic logic families. At VTH point any small variation in the input nodes would cause a fast variation of the voltage at the output node. In all other logic families for the output node to begin transition, the inputs need to cross the threshold voltage. Furthermore, when the valid inputs to a gate are asserted, the gate outputs will only need to make a partial transition from VTH to VOH or VOL. The higher speed of the proposed logic is due to the reduction in both low-to-high and high-to-low propagation time delays. The main challenge in the design of circuits based on the proposed logic family is, however, maintaining the VTH stability for long cascaded circuit structures, which is the key factor in the fast logic evaluation and high performance of the proposed circuits. 3. Performance results 3.1. Proposed circuit structures To provide a trade-off between the performance and power consumption, two basic structures are proposed in this paper. These structures are shown in Fig. 2. Two structures are derived from two logic families; the pseudo-NMOS (for high speed applications, Fig. 2(a) and (b) and the standard fully complementary CMOS (for low power applications, Fig. 2(c) and (d). Each of these basic structures can operate in two configurations: with reset phase voltage set to 0 (Vres=0) or Vcc/2 (Vres=Vcc/2). With reference to Fig. 1(c), we observe that the initial stages have a different behavior from the other stages, as they never have enough time to reach to the VTH point. However, with Vres=Vcc/2, dissimilarity in the voltages in the initial stages is removed. Display Full Size version of this image (32K)Fig. 2. Proposed structures: (a) HS0: high speed structure with Vres=0; (b) HS06: high speed structure with Vres=Vcc/2; (c) LP0: low power structure with Vres=0; and (d) LP06: low power structure with Vres=Vcc/2. 3.2. Comparison of the proposed structure vs. the dynamic domino CMOS To compare the proposed structures against the dynamic domino CMOS structures, the behavior of a long chain of inverters is simulated. We used a CMOS process from UMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at . The values of propagation time delay, tp, for low-to-high and high-to-low transitions, obtained from the simulation for 20 stages, are shown in Table 1. Table 1 also shows the average values of tp and the speed up (tp ratio) with respect to the dynamic domino logic, standard CMOS, pseudo-NMOS. Table 1. Simulation results for circuit delay parameter for the standard CMOS, pseudo-NMOS, domino and the proposed structure (20 inverters) ParameterCMOSProposed LP0Proposed LP06Pseudo NMOSDominoProposed HS0Proposed HS06tplh (ns)2.2340.8630.7761.8230.6200.401tphl (ns)2.2470.7890.6811.8612.5950.6900.468tp (ns)2.2400.8260.7281.8422.5950.6550.434tp ratio0.9473.1423.5651.40913.9625.979For the proposed structure to work in circuits with large number of stages, special care must be taken to avoid dissimilar capacitive loads in all the intermediate stages. This will ensure that all nodes rise together to the threshold voltage VTH. The effect of dissimilar capacitive l