硬件设计技术.ppt

,I,I,I,I,I,HARDWARE D ESIGN TECHNIQUES,SECTION 10,HARDWARE DESIGN TECHNIQUES,Low Voltage Interfaces,Grounding in Mixed Signal Systems,Digital Isolation Techniques,Power Supply Noise Reduction and Filtering,Dealing with High Speed Logic,10.a,HARDWARE D ESIGN TECHNIQUES,10.b,HARDWARE D ESIGN TECHNIQUES,SECTION 10,HARDWARE DESIGN TECHNIQUESWalt Kester,LOW V OLTAGE INTERFACES,Ethan Bordeaux,Johannes Horvath,Walt Kester,For the past 30 years,the standard VDD for digital circuits has been 5V.This voltagelevel was used because bipolar transistor technology required 5V to allow headroomfor proper operation.However,in the late 1980s,Complimentary Metal OxideSemiconductor(CMOS)became the standard for digital IC design.This process didnot necessarily require the same voltage levels as TTL circuits,but the industryadopted the 5V TTL standard logic threshold levels to maintain backwardcompatibility with older systems(Reference 1).,The current revolution in supply voltage reduction has been driven by demand forfaster and smaller products at lower costs.This push has caused silicon geometriesto drop from 2m in the early 1980s to 0.25m that is used in todays latestmicroprocessor and IC designs.As feature sizes have become increasingly smaller,the voltage for optimum device performance has also dropped below the 5V level.This is illustrated in the current microprocessors for PCs,where the optimum coreoperating voltage is programmed externally using voltage identification(VID)pins,and can be as low as 1.3V.,The strong interest in lower voltage DSPs is clearly visible in the shifting salespercentages for 5V and 3.3V parts.Sales growth for 3.3V DSPs has increased atmore than twice the rate of the rest of the DSP market(30%for all DSPs versusmore than 70%for 3.3V devices).This trend will continue as the high volume/highgrowth portable markets demand signal processors that contain all of the traits ofthe lower voltage DSPs.,On the one hand,the lower voltage ICs operate at lower power,allow smaller chipareas,and higher speeds.On the other hand,the lower voltage ICs must ofteninterface to other ICs which operate at larger VDD supply voltages thereby causinginterface compatibility problems.Although lower operating voltages mean smallersignal swings,and hence less switching noise,noise margins are lower for lowsupply voltage ICs.,The popularity of 2.5V devices can be partially explained by their ability to operatefrom two AA alkaline cells.Figure 10.2 shows the typical discharge characteristicsfor a AA cell under various load conditions(Reference 2).Note that at a load currentof 15mA,the voltage remains above+1.25V(2.5V for two cells in series)for nearly100 hours.Therefore,an IC that can operate effectively at low currents with asupply voltage of 2.5V 10%(2.25V-2.75V)is very useful in portable designs.Also,DSPs that have low mA/MIPS ratings and can integrate peripherals onto a singlechip,such as the ADSP-218x L or M-series,are useful in portable applications.,10.1,HARDWARE D ESIGN TECHNIQUES,LOW VOLTAGE MIXED-SIGNAL ICs,I Lower Power for Portable Applications,I 2.5V ICs Can Operate on Two“AA”Alkaline CellsI Faster CMOS Processes,Smaller Geometries,Lower,Breakdown Voltages,I Multiple Voltages in System:+5V,+3.3V,+2.5V,+1.8V,DSP Core Voltage(VID),Analog Supply Voltage,I Interfaces Required Between Multiple Logic TypesI Lower Voltage Swings Produce Less Switching NoiseI Lower Noise Margins,I Less Headroom in Analog Circuits Decreases Signal Swings,and Increases Sensitivity to Noise(But thats the subject of anentire seminar!),Figure 10.1,DURACELL MN1500“AA”ALKALINE BATTERY,DISCHARGE CHARACTERISTICS,VOLTAGE,(V),1.25,SERVICE HOURS,Courtesy:Duracell,Inc.,Berkshire Corporate Park,Bethel,CT 06801,http:/,Figure 10.2,10.2,HARDWARE D ESIGN TECHNIQUESIn order to understand the compatibility issues relating to interfacing ICs operatedat different VDD supplies,it is useful to first look at the structure of a typical CMOSlogic stage as shown in Figure 10.3.TYPICAL CMOS IC OUTPUT DRIVER CONFIGURATION,VDD,High=“1”,VDD,VDDPMOS,High=“1”,VDD,VIH MIN,INPUT,PREDRIVERLOGIC,OUTPUT,VOH MIN,VIL MAX,NMOS,0V,Low=“0”,Low=“0”,VOL MAX0V,VIL MAX=Maximum Allowable Input Low Logic LevelVIH MIN=Minimum Allowable Input High Logic LevelVOL MAX=Maximum Allowable Output Low Logic LevelVOH MIN=Minimum Allowable Output High Logic LevelFigure 10.3Note that the output driver stage consists of a PMOS and an NMOS transistor.When the output is high,the PMOS transistor connects the output to the+VDDsupply through its low on-resistance(RON),and the NMOS transistor is off.Whenthe output is low,the NMOS transistor connects the output to ground through itson-resistance,and the PMOS transistor is off.The RON of a CMOS output stage canvary between 5 and 50 depending on the size of the transistors,which in turn,determines the output current drive capability.A typical logic IC has its power supplies and grounds separated between the outputdrivers and the rest of the circuitry(including the pre-driver).This is done tomaintain a clean power supply,which reduces the effect of noise and ground bounceon the I/O levels.This is increasingly important,since added tolerance andcompliance are critical in I/O driver specifications,especially at low voltages.Figure 10.3 also shows“bars”which define the minimum and maximum requiredinput and output voltages to produce a valid high or low logic level.Note that forCMOS logic,the actual output logic levels are determined by the drive current andthe RON of the transistors.For light loads,the output logic levels are very close to 0Vand+VDD.The input logic thresholds,on the other hand,are determined by theinput circuit of the IC.There are three sections in the“input”bar.The bottom section shows the inputrange that is interpreted as a logic low.In the case of 5V TTL,this range would be10.3,2.5VJEDECoutput,(-1mA),5VTTLoutput,(-2mA),3.3VLVTTLinput,3.3VLVTTLoutput,(-2mA),2.5VJEDECinput,5VCMOSinput,5VCMOSoutput,(20uA),2.5VVCXinput,5VTTLinput,2.5VVCXoutput,(-12mA),HARDWARE D ESIGN TECHNIQUESbetween 0V and 0.8V.The middle section shows the input voltage range where it isinterpreted as neither a logic low nor a logic high.The upper section shows wherean input is interpreted as a logic high.In the case of 5V TTL,this would be between2V and 5V.Similarly,there are three sections in the“output”bar.The bottom range shows theallowable voltage for a logic low output.In the case of 5V TTL,the IC must output avoltage between 0V and 0.4V.The middle section shows the voltage range that isnot a valid high or low-the device should never transmit a voltage level in thisregion except when transitioning from one level to the other.The upper sectionshows the allowable voltage range for a logic high output signal.For 5V TTL,thisvoltage is between 2.4V and 5V.The chart does not reflect a 10%overshoot/undershoot also allowed on the inputs of the logic standard.A summary of the existing logic standards using these definitions is shown inFigure 10.4.Note that the input thresholds of classic CMOS logic(series-4000,forexample)are defined as 0.3VDD and 0.7VDD.However,most CMOS logic circuits inuse today are compatible with TTL and LVTTL levels which are the dominant 5Vand 3.3V operating standards for DSPs.Note that 5V TTL and 3.3V LVTTL inputand output threshold voltages are identical.The difference is the upper range forthe allowable high levels.LOW VOLTAGE LOGIC LEVEL STANDARDS,VOLTS5.0,5V CMOS,5V TTL,4.54.0,I,O,I,O,I=INPUTO=OUTPUT,3.5,3.3V LVTTL,2.5V VCX,3.0,I,O,2.5V JEDEC,2.52.0,I,O,I,O,1.51.00.50Figure 10.410.4,HARDWARE D ESIGN TECHNIQUES,The international standards bureau JEDEC(Joint Electron Device EngineeringCouncil)has created a 2.5V standard(JEDEC standard 8-5)which will most likelybecome the minimum requirement for 2.5V operation(Reference 3).However,thereis no current(2000)dominant 2.5V standard for IC transmission and reception,because few manufacturers are making products that operate at this voltage.Thereis one proposed 2.5V standard created by a consortium of IC manufacturers,titledthe Low Voltage Logic Alliance.Their specification provides a guideline forsemiconductor operation between 1.8V and 3.6V.A standard covering this voltagerange is useful because it ensures present and future compatibility.As an example,the 74VCX164245,a bus translator/transceiver from Fairchild Semiconductor,isdesigned to be operated anywhere between 1.8V-3.6V and has different input andoutput characteristics depending upon the supplied VDD.This standard,namedVCX,was formed by Motorola,Toshiba and Fairchild Semiconductor.It currentlyconsists primarily of bus transceivers,translators,FIFOs and other building blocklogic.There are also a wide range of other low voltage standards,such as GTL(Gunning Transceiver Logic),BTL(Backplane Transceiver Logic),and PECL(PseudoECL Logic).However,most of these standards are aimed at applicationspecific markets and not for general purpose semiconductor systems.,The VCX devices can be operated on a very wide range of voltage levels(1.8V-3.6V).The I/O characteristics of this standard are dependent upon the VDD voltageand the load on each pin.In Figure 10.4,one voltage(2.5V)was chosen to show thegeneral I/O behavior of a VCX device.Each of the devices output voltages is listedfor a specific current.As the current requirements increase,the output high voltagedecreases while the output low voltage increases.Please refer to the appropriatedata sheets for more specific I/O information.,From this chart,it is possible to visualize some of the possible problems inconnecting together two ICs operating on different standards.One example wouldbe connecting a 5V CMOS device to a 3.3V LVTTL IC.The 5V CMOS high level istoo high for the LVTTL to handle(3.3V).This could cause permanent damage tothe LVTTL chip.Another possible problem would be a system with a 2.5V JEDECIC driving a 5V CMOS device.The logic high level from the 2.5V device is not highenough for it to register as a logic high on the 5V CMOS input(VIH MIN=3.5V).These examples illustrate two possible types of logic level incompatibilities-eithera device being driven with too high a voltage or a device not driving a voltage highenough for it to register a valid high logic level with the receiving IC.Theseinterfacing problems introduce two important concepts:voltage tolerance andvoltage compliance.,V OLTAGE TOLERANCE AND V OLTAGE COMPLIANCE,A device that is voltage tolerant can withstand a voltage greater than its VDD on itsI/O pins.For example,if a device has a VDD of 2.5V and can accept inputs equal to3.3V and can withstand 3.3V on its outputs,the 2.5V device is called 3.3V tolerant.The meaning of input voltage tolerance is fairly obvious,but the meaning of outputvoltage tolerance requires some explanation.The output of a 2.5V CMOS driver inthe high state appears like a small resistor(RON of the PMOS FET)connected to2.5V.Obviously,connecting its output directly to 3.3V is likely to destroy the devicedue to excessive current.However,if the 2.5V device has a three-state output whichis connected to a bus which is also driven by a 3.3V IC,then the meaning becomes,10.5,HARDWARE D ESIGN TECHNIQUES,clearer.Even though the 2.5V IC is in the off(third-state)condition,the 3.3V IC candrive the bus voltage higher than 2.5V,potentially causing damage to the 2.5V ICoutput.,A device which is voltage compliant can receive signals from and transmit signals toa device which is operated at a voltage greater than its own VDD.For example,if adevice has a 2.5V VDD and can transmit and receive signals to and from a 3.3Vdevice,the 2.5V device is said to be 3.3V compliant.,The interface between the 5V CMOS and 3.3V LVTTL parts illustrates a lack ofvoltage tolerance;the LVTTL IC input is overdriven by the 5V CMOS device output.The interface between the 2.5V JEDEC and the 5V CMOS part demonstrates a lackof voltage compliance;the output high level of the JEDEC IC does not comply to theinput level requirement of a the 5V CMOS device.,LOGIC VOLTAGE TOLERANCE,AND COMPATIBILITY DEFINITIONS,I Voltage Tolerance:,N A device that is Voltage Tolerant can withstand a voltagegreater than its VDD on its input and output pins.If a devicehas a VDD of 2.5V and can accept inputs of 3.3V(10%),the,2.5V device is 3.3V tolerant on its input.Input and outputtolerance should be examined and specified separately.,I Voltage Compliance:,N A device that is Voltage Compliant can transmit and receive,signals to and from logic which is operated at a voltage,greater than its own VDD.If a device has a 2.5V VDD and can,properly transmit signals to and from 3.3V logic,the 2.5Vdevice is 3.3V compliant.Input and output compliance shouldbe examined and specified separately.,Figure 10.5,I NTERFACING 5V TO 3.3V S YSTEMS USING NMOS FET BUSSWITCHES,When combining ICs that operate on different voltage standards,one is often forcedto add additional discrete elements to ensure voltage tolerance and compliance.Inorder to achieve voltage tolerance between 5V and 3.3V logic,for instance,a busswitch voltage translator,or QuickSwitch can be used(Reference 4,5).The busswitch limits the voltage applied to an IC.This is done to avoid applying a largerinput high voltage than the receiving device can tolerate.,As an example,it is possible to place a bus switch between a 5V CMOS and 3.3VLVTTL IC,and the two devices can then transmit data properly as shown in Figure10.6.The bus switch is basically an NMOS FET.If 4.3V is placed on the gate of theFET,the maximum passable signal is 3.3V(approximately 1V less than the gate,10.6,HARDWARE D ESIGN TECHNIQUESvoltage).If both input and output are below 3.3V,the NMOS FET acts as a lowresistance(RON 5).As the input approaches 3.3V,the FET on-resistanceincreases,thereby limiting the signal output.The QuickSwitch contains 10 bi-directional FETs with a gate drive enable as shown in Figure 10.6.The VCC of theQuickSwitch sets the high level for the gate drive.One way of creating a 4.3V supply on a 5V/3.3V system board is to place a diodebetween the 5V supply and VCC on the QuickSwitch.In Figure 10.6,the 4.3V isgenerated by a silicon diode in series with a Schottky diode connected to the 3.3Vsupply.With 10%tolerances on both 5V and 3.3V supplies,this method produces amore stable gate bias voltage.Some bus switches are designed to operate on either3.3V or 5V directly and generate the internal gate bias level internally.A QuickSwitch removes voltage tolerance concerns in this mixed logic design.Oneconvenient feature of bus switches is that they are bi-directional;this allows thedesigner to place a bus translator between two ICs and not have to create additionalrouting logic for input and output signals.+3.3V/+5V BIDIRECTIONAL INTERFACE USINGNMOS FET ACHIEVES VOLTAGE TOLERANCE,+3.3V BUS,1V,+4.3V,470 k,+5V BUS,Si SCHOTTKY0.1F,3.3V 10%,5V 10%,LOGIC,NMOSRON=5,LOGIC,“1”=DISABLE“0”=ENABLE,0V/VCC,QS3384 QuickSwitch,10 SWITCHES/PACKAGEOPERATE WITH QS3384 VCC=+4.3VFigure 10.6A bus swi