数字逻辑设计及应用24课件.ppt
Chapter 8 Sequential Logic Design Practices ( 时序逻辑设计实践),SSI Latches and Flip-Flops (SSI型锁存器和触发器)MSI Device: Counters, Shift Registers (MSI器件：计数器、移位寄存器)Others: Documents, Iterative, Failure and Metastability (其它：文档、迭代、故障和亚稳定性),Digital Logic Design and Application (数字逻辑设计及应用),1,Chapter 8 Sequential Logic Des,Review of Last Class (内容回顾),Sequential-Circuit Documentation Standards (时序电路文档标准)Timing Diagrams and Specifications ( 定时图及其规范 ),Digital Logic Design and Application (数字逻辑设计及应用),2,Review of Last Class (内容回顾)Seq,Review of Last Class (内容回顾),Latches and Flip-Flops (锁存器和触发器)SSI Latches and Flip-Flops (SSI型锁存器和触发器)Applications: Switch Debouncing, Bus Holder (应用：开关消抖、总线保持)Multibit Registers and Latches( 多位寄存器和锁存器 ),Digital Logic Design and Application (数字逻辑设计及应用),3,Review of Last Class (内容回顾)Lat,8.4 Counter (计数器),Modulus: The number of states in the cycle （模：循环中的状态个数）A modulo-m counter, or sometimes, a divide-by-m counter ( 模m计数器, 又称 m分频计数器）,Any clock sequential circuit whose state diagramContain a Single cycle.(状态图中包含有一个循环的任何时钟时序电路),Digital Logic Design and Application (数字逻辑设计及应用),4,8.4 Counter (计数器)Modulus: The,8.4 Counter (计数器),An n-bit binary counter (n位二进制计数器),Digital Logic Design and Application (数字逻辑设计及应用),5,8.4 Counter (计数器)An n-bit bin,A Synchronous Binary Up Counter(同步二进制加法计数器),在多位二进制数的末位加 1，仅当第 i 位以下的各位都为 1 时，第 i 位的状态才会改变。最低位的状态每次加1都要改变。,Qi* = (Qi-1 Q1 Q0) Qi,Q0* = 1 Q0,Digital Logic Design and Application (数字逻辑设计及应用),6,A Synchronous Binary Up Counte,A Synchronous Binary Up-Counter(同步二进制加法计数器),利用有使能端的 T 触发器实现：,Q* = EN Q,ENi = Qi-1 Qi-2 Q1 Q0,利用 D 触发器实现：,Di = (Qi-1 Q1 Q0) Qi,Qi* = (Qi-1 Q1 Q0) Qi,Q0* = 1 Q0,Digital Logic Design and Application (数字逻辑设计及应用),7,A Synchronous Binary Up-Counte,MSI Counters (MSI计数器),74x161、74x1634-Bit Binary Up-Counters (with Asynchronous/Synchronous Clear) (4位二进制加法计数器（异、同步清零）)74x160、74x1621-Bit Decade (BCD Code) Up-Counters (with Asynchronous/Synchronous Clear)(1位十进制（BCD）加法计数器（异、同步清零）),Digital Logic Design and Application (数字逻辑设计及应用),8,MSI Counters (MSI计数器)74x161、74,MSI Counter (MSI计数器),74x1694-Bit Binary Up/Down Counter(4位二进制可逆计数器)计数器可以用作分频器,Digital Logic Design and Application (数字逻辑设计及应用),9,MSI Counter (MSI计数器)74x169Digi,Any Modulus Counter(任意模值计数器),利用SSI器件构成 时钟同步状态机设计利用MSI计数芯片构成 利用n位二进制计数器实现模m计数器分两种情况考虑： m 2n, 清零法、置数法,Digital Logic Design and Application (数字逻辑设计及应用),10,Any Modulus Counter(任意模值计数器)利,Any Modulus Counter(任意模值计数器),Realize a Modulo-m Counter with an n-bit Binary Counter (利用n位二进制计数器实现模m计数器),Digital Logic Design and Application (数字逻辑设计及应用),11,Any Modulus Counter(任意模值计数器)D,Any Modulus Counter(任意模值计数器),Consider two cases(分两种情况考虑)： m 2n,清零法、置数法,级联。,Digital Logic Design and Application (数字逻辑设计及应用),12,Any Modulus Counter(任意模值计数器)C,Cascading Counter (计数器的级联),思考：利用低位的进位控制高位的时钟行不行？,Digital Logic Design and Application (数字逻辑设计及应用),13,Cascading Counter (计数器的级联)CLOC,Modulo-m Counter(模m计数器（ m 2n）),先进行级联，再整体置零或预置数例：用74x163构造模193计数器 两片163级联得8位二进制计数器（0255） 采用整体清零法，0192 采用整体预置数法，63255 25619363若 m 可以分解：m = m1m2分别实现m1和m2，再级联,Digital Logic Design and Application (数字逻辑设计及应用),14,Modulo-m Counter(模m计数器（ m 2,6310 = ( 0011 1111 )2,Digital Logic Design and Application (数字逻辑设计及应用),15,6310 = ( 0011 1111 )2 CLK74x1,Digital Logic Design and Application (数字逻辑设计及应用),16,CLK74x163 CLK74x16311CLOCKC,Analysis what the modulo of the following circuit is ?(分析下面的电路的模为多少？),QD QC QB QA0 0 0 00 1 1 00 1 1 11 0 0 01 1 1 01 1 1 1,Digital Logic Design and Application (数字逻辑设计及应用),17,Analysis what the modulo of th,Exercise： Analysis what the modulo of the following circuit is ? (练习:分析下面的电路的模为多少？) ？,模12计数器QD：12分频占空比50,Digital Logic Design and Application (数字逻辑设计及应用),18,Exercise： Analysis what the mo,8.5 Shift Register（移位寄存器）,Serial-In,Serial-Out(串入串出移位寄存器),Can be used to delay aSignal by n clock ticks(可以使一个信号延迟n 个时钟周期之后再输出),Digital Logic Design and Application (数字逻辑设计及应用),19,8.5 Shift Register（移位寄存器）Seri,Serial-In, Parallel-Out Shift Register(串入并出移位寄存器),Can be used to perform Serial-to-Parallel Conversion(可以用来完成串并转换),Digital Logic Design and Application (数字逻辑设计及应用),20,Serial-In, Parallel-Out Shift,Parallel-In, Serial-Out (并入串出移位寄存器),多路复用结构,SERIN,Digital Logic Design and Application (数字逻辑设计及应用),21,Parallel-In, Serial-Out (并入串出移,Parallel-In, Parallel-Out (并入并出移位寄存器),SERIN,Digital Logic Design and Application (数字逻辑设计及应用),22,Parallel-In, Parallel-Out (并入并,8.5.2 MSI Shift Register (MSI移位寄存器),Digital Logic Design and Application (数字逻辑设计及应用),23,8.5.2 MSI Shift Register (M,4-Bit Universal Shift Register (4位通用移位寄存器74x194),Left Shift Input:From QD to QA (左移输入),Right Shift Input:From QA to QD(右移输入),Digital Logic Design and Application (数字逻辑设计及应用),24,4-Bit Universal Shift Registe,保持,Figure 8-41,Qi* = S1S0Qi + S1S0Qi-1 + S1S0Qi+1 + S1S0INi,Digital Logic Design and Application (数字逻辑设计及应用),4-Bit Universal Shift Register (4位通用移位寄存器74x194),25,00S1S0保持S1 S0S1 S010左移0,Use Bidirectional Three-State lines for Input and output(输入输出采用双向三态数据线),Digital Logic Design and Application (数字逻辑设计及应用),8-Bit Universal Shift Register (8位通用移位寄存器),26,S1 S0 功能0 0 保持LIN,CLKCLRS1S0,LIN,RIN,移位寄存器的扩展,27,CLK74x194 CLKCLKLINRIN移Para,8.5.3 Shift-Register Counters(移位寄存器计数器),D0 = F ( Q0 , Q1 , , Qn-1 ),Feedback Logic (反 馈 逻 辑),General Structure (一般结构)：,Digital Logic Design and Application (数字逻辑设计及应用),28,8.5.3 Shift-Register Counters,1000,0100,0001,0010,8.5.4 Ring Counters (环型计数器),D0 D1 D2 D3, 非自启动的,无效状态,D0 = Qn-1,29,1000010000010010有效状态其他状态8.5.4,自启动的自校正的,Digital Logic Design and Application (数字逻辑设计及应用),30,有效状态无效状态D QD QD,8.5.5 Twisted-Ring Counters（扭环计数器）,D0 = Qn-1,0000,1000,1100,1110,1111,0111,0011,0001,无效,Normal State Cycle (有效的状态循环),Self-correcting(自校正）,Johnson, Moebius Counter,31,8.5.5 Twisted-Ring Counters（扭,第8章 作业,8.13(8.13)8.16(8.14) 8.18(8.16)8. 36(8.35) 8. 39(8.38) 8.41(8.42)8.46(8.46),Digital Logic Design and Application (数字逻辑设计及应用),32,第8章 作业8.13(8.13)Digital Logi,
